Technical Field
The present disclosure relates to converters and, more particularly, to a control device for a quasi-resonant high-power-factor AC/DC converter.
Description of the Related Art
High-Power-Factor (Hi-PF) Quasi-resonant (QR) flyback converters are a common choice in a number of cost-sensitive applications, such as solid-state lighting (SSL). Power converters are often powered from the ac power line, and many applications should also meet both the IEC60950 regulation on electrical safety and the IEC61000-3-2 regulation on the limits for harmonic current emissions. In fact, they are able to generate a bus voltage isolated from the power line to meet IEC60950, and draw a current with low harmonic content to meet IEC61000-3-2 with a single conversion stage.
A considerable number of Power Factor Control (PFC) control chips implementing QR operation (e.g. Transition Mode, Boundary Mode or Critical Mode) are commercially available. Although primarily conceived for controlling PFC converters using boost topology, they can be successfully used to control Hi-PF QR flyback converters as well.
A Hi-PF flyback converter is powered from the ac power line with no energy reservoir capacitor after the input bridge rectifier, thus its input voltage is basically a rectified sinusoid (Vin(θ)=VPK|sin θ|) and the current drawn from the power line is sinusoidal-like.
A flyback converter (whether Hi-PF or not) is said to be QR-operated when the turn-on of the power switch, often a MOSFET, is synchronized to the instant the transformer demagnetizes, when the secondary current has become zero, normally after an appropriate delay. This allows the turn-on to occur on the valley of the drain voltage ringing that follows the demagnetization, therefore reducing turn-on losses. For this reason this operation is often termed “valley-switching”. Most commonly, peak current mode control is used, so the turn-off of the power switch is determined by the current sense signal reaching the value programmed by the control loop that regulates the output voltage or current.
FIG. 1 shows a Hi-PF QR flyback converter 20 according to the prior art. On the primary side, the flyback converter 20 comprises a bridge rectifier 22 having the ac power line at its input 24. A capacitor Cin, which serves as a high-frequency smoothing filter, is connected across the output terminals of the bridge rectifier 22, with the negative terminal connected to ground and the positive terminal connected to a primary winding Lp of a transformer 26. The transformer 26 also has an auxiliary winding Laux, and a secondary winding Ls. A power switch M has its drain terminal tied to the primary winding Lp, and its source terminal connected to ground via a resistor Rs. The resistor Rs allows a reading of the current flowing through the power switch M, which is representative of the current flowing through Lp when M is ON. The primary side of the converter also includes a resistive voltage divider, made up of resistors Ra and Rb connected in parallel with the capacitor Cin, and a clamp circuit 27 that clamps the spikes on the drain voltage due to the leakage inductance of the primary winding Lp.
On the secondary side of the transformer 26, the secondary winding Ls has one end connected to the secondary ground and the other end connected to the anode of a diode D. The diode D has its cathode connected to the positive plate of a capacitor Cout that has its negative plate connected to the secondary ground.
This flyback converter 20 generates at its output terminals across Cout a dc voltage Vout that will supply the load. Assuming an SSL application, the load will be a string of high-brightness LEDs.
The converter is closed-loop controlled isolated converter in which the quantity to be regulated (either the output voltage Vout or the output current Iout) is compared to a reference value and an error signal is generated depending on the difference between the regulated quantity and the reference value. This error signal is transferred to the primary side, typically with an optocoupler, which is not shown in FIG. 1. On the primary side, this error signal is represented by a current IFB that is sunk from a dedicated pin FB in a controller 29, producing a control voltage Vc on the pin FB. The controller 29 drives the power switch M based in part on the control voltage Vc. The control voltage Vc can be regarded as a dc level if the open-loop bandwidth of the overall control loop, which is determined by a frequency compensation network located inside an isolated feedback block 28, is narrow enough, typically below 20 Hz, and a steady-state operation is assumed.
The control voltage Vc is internally fed into one input of a multiplier block 30. The multiplier 30 also receives a portion of the instantaneous rectified line voltage sensed across Cin, which is divided at a resistor divider Ra−Rb. The divider ratio Rb/(Ra+Rb) will be denoted with Kp.
The output of the multiplier block 30 is the product of a rectified sinusoid times a dc level, then still a rectified sinusoid whose amplitude depends on the rms line voltage and the amplitude of the control voltage Vc. The multiplier 30 output signal will be a voltage reference signal VCS,REF(θ) for the peak primary current.
The output signal of the multiplier 30 is fed to the inverting input of a comparator 32 that receives at its non-inverting input the sensing signal VCS(t,θ) that is sensed across the sense resistor Rs. The sensing signal VCS(t, θ) is proportional to the instantaneous current Ip(t,θ) flowing through the primary winding Lp and the power switch M when the power switch M is ON. Assuming the power switch M is initially ON, the current through the primary winding Lp will be ramping up and so will the voltage across the resistor Rs. A SR flip-flop 34 has an output Q that is coupled to a driver 35, which drives the power switch M. When VCS(t,θ) equals VCS,REF(θ) the comparator 32 resets the SR flip-flop 34, and the power switch M is switched off Therefore, the reference voltage signal VCS, REF(θ) from the multiplier 30, which is shaped as a rectified sinusoid, determines the peak value of the primary current, which will be enveloped by a rectified sinusoid.
After the power switch M has been switched off, the energy stored in the primary winding Lp is transferred by magnetic coupling to the secondary winding Ls and then dumped into the output capacitor Cout and the load until the secondary winding Ls is completely demagnetized. At this point, the diode D opens and the drain node, which was fixed at Vin(θ)+VR while Ls and D were conducting, becomes floating. The drain node's voltage tends to eventually reach the instantaneous line voltage Vin(θ) through a damped ringing due to its parasitic capacitance that starts resonating with Lp. However, the quick drain voltage fall that follows the transformer 26 demagnetizing is coupled to the pin ZCD of the controller through the auxiliary winding Laux and the resistor RZCD. A zero-crossing detector (ZCD) 36 releases a pulse every time it detects a negative-going edge falling below a threshold, and this pulse sets the SR flip-flop 34 and drives the ON the power switch M, starting a new switching cycle.
An OR gate 38 between the ZCD 36 and the set input of the SR flip-flop 34 allows the output of a STARTER block 40 to initiate a switching cycle. The starter block 40 produces a signal at power-on when no signal is available on the input pin ZCD and prevents the converter 20 from getting stuck in case the signal on the input pin ZCD is lost for any reason.
Assuming θε(0,π), according to the control scheme under consideration the peak envelope of the primary current is given by:Ipkp(θ)=Ip(TON,θ)=IPKp sin θ.  (1)
It is worth noticing that this scheme results in a constant ON-time TON of the power switch M:
                                          T            ON                    =                                    Lp              ⁢                                                                    I                    PKp                                    ⁢                  sin                  ⁢                                                                          ⁢                  θ                                                                      V                    PK                                    ⁢                  sin                  ⁢                                                                          ⁢                  θ                                                      =                          Lp              ⁢                                                I                  PKp                                                  V                  PK                                                                    ,                            (        2        )            
For simplicity, the OFF-time of the power switch, TOFF(θ), will be considered coincident with the time TFW(θ) during which current circulates on the secondary side. In other words, the time interval TR during which the voltage across the primary switch rings until reaching the valley of the ringing will be neglected. This is acceptable as long as TR<<TOFF(θ).
The switching period T(θ) is therefore given by:T(θ)=TON+TFW(θ).  (3)Considering volt-second balance across the primary inductor it is possible to write:
                                          T            FW                    ⁡                      (            θ            )                          =                              T            ON                    ⁢                                                                      V                  PK                                ⁢                sin                ⁢                                                                  ⁢                θ                                            V                R                                      .                                              (        4        )            
where VR is the reflected voltage, i.e. the output voltage Vout times the primary-to-secondary turns ratio n=Np/Ns, seen across the primary winding Lp of the transformer 26 in the time interval TFW(θ):VR=n(Vout+VF)  (5)wherein VF is the forward drop on the secondary rectifier. Therefore, T(θ) can be rewritten as:T(θ)=TON(1+Kv sin θ).  (6)
with Kv=VPK/VR.
The input current Iin(θ) to the converter is found by averaging the primary current Ip(t,θ) over a switching cycle. The primary current Ip(t,θ) is the series of gray triangles in the right-hand side diagram of FIG. 2 so, taking equation (1) into account, it is found that:
                                          I            in                    ⁡                      (            θ            )                          =                                            1              2                        ⁢                                          I                pkp                            ⁡                              (                θ                )                                      ⁢                                          T                ON                                            T                ⁡                                  (                  θ                  )                                                              =                                    1              2                        ⁢                          I              PKp                        ⁢                                                            sin                  ⁢                                                                          ⁢                  θ                                                  1                  +                                                            K                      v                                        ⁢                    sin                    ⁢                                                                                  ⁢                    θ                                                              .                                                          (        7        )            
Equation (7) shows that the input current is not a pure sinusoid. The function sin θ/(1+Kv sin θ), plotted in FIG. 3a for different values of Kv, is a periodic even function, at twice the line frequency. Conversely, the current drawn from the mains will be its “odd counterpart”, at the line frequency, as shown in FIG. 3b. 
This current is sinusoidal only for Kv=0. When Kv≠0, although a sinusoidal-like shape is maintained, the input current is distorted, the higher Kv the higher the distortion. Since Kv cannot be zero (which would require the reflected voltage to tend to infinity), the obvious conclusion is that this QR control scheme does not permit zero Total Harmonic Distortion (THD) of the input current nor unity power factor in a flyback converter even in the ideal case, unlike boost topology.
FIG. 4 shows the plots of the THD of the input current and of the Power Factor vs. Kv.
Although the distortion is significant, especially at high line (i.e. high Kv) the individual harmonics are still well within the limits considered by the regulation on the limits for harmonic current emissions, the IEC61000-3-2 (or its Japanese homologous, the JEIDA-MITI). An example of harmonic measurements on a real-world application is shown in FIG. 5. For this reason the Hi-PF QR flyback converter is currently widely used, especially in solid state lighting (SSL) applications where safety isolation from the power line is required by regulations. These include LED drivers from a few watts to tens of watts for residential and professional lighting.
Still considering the SSL market, this inherent distortion is a significant problem. In fact, as shown in the plot of FIG. 4, it is difficult to meet the target THD<10% (or even lower) that is becoming a market requirement in some geographical areas. Low values of Kv should be used even at high line, which means a high reflected voltage VR. Because the power MOSFET in a flyback converter has to be rated for a breakdown voltage significantly larger than VPKmax+VR, in principle a high VR requires a high voltage rating MOSFET, which is more expensive and has higher parasitic losses. In practice, to meet the target, VR might be so high that a MOSFET with adequate voltage rating could be prohibitive in terms of cost or originate too much power loss, or even be unavailable.
In the literature it is reported that a Hi-PF flyback converter operated in Discontinuous Conduction Mode (DCM) with a fixed switching frequency has no inherent distortion of the input current. Specifically, it is demonstrated that, operating in that way, the shape of the input current tracks that of the input voltage provided the quantity D2T, where D is the duty cycle of the power switch and T the switching period, is constant along each line half-cycle under steady-state conditions. With a fixed switching period T, keeping the duty cycle D constant along a line half-cycle meets the control goal.
By definition, this provides unity power factor and, with a sinusoidal input voltage, a sinusoidal input current. This approach is used in commercial products.
However, there are a few benefits in using QR operation that are lost when operating in DCM with a fixed frequency (FF).
First, QR operation results in lower conducted electromagnetic interference (EMI) emissions. Due to the sinusoidal input voltage, the switching frequency is modulated at twice the line frequency fL. This causes the spectrum to be spread over frequency bands, rather than being concentrated on single frequency values. Especially when measuring conducted emissions with the average detection method, the level reduction can be of several dBμV. It is then possible to reduce the size and the cost of the EMI filter.
Second, QR operation gives safer operation under short circuit conditions. The conduction cycles of the power switch (MOSFET) start only when the transformer is fully demagnetized, so flux runaway and, therefore, transformer saturation are not possible. Moreover, during a short circuit the demagnetization voltage is very low, so the time needed for the transformer to demagnetize becomes very long and the converter works at low frequency with a small duty cycle. As a result, the power that the converter is able to carry is very low.
Finally, QR operation results in higher efficiency. With QR operation the converter works very close to the DCM-CCM (Continuous Conduction Mode) boundary. The form factor (i.e. the ratio of the rms to the dc value) of both the primary and the secondary currents is generally smaller with respect to FF operation where the converter can work deep in DCM. Consequently, for a given throughput, power conduction losses are lower with QR. Additionally, QR allows valley-switching or even true soft-switching (zero-voltage switching, ZVS, when VPK<VR), which minimizes turn-on losses in the power switch (MOSFET).